Synthesis of Steel-ASIC, a RISC-V Core

It is presented the design flow of an ASIC version STEEL, a RISC-V microprocessor developed at UFRGS. The core called STEEL implements RV32I and Zicsr instruction sets specifications. whole process entails logical physical synthesis, using X-Fab 180 nm, which relies on Cadence EDA framework. circuit operates with maximum frequency 19.61 MHz estimates obtained from synthesis indicates power consumption 10.09 mW.